OVERVIEW

What is Arm NoC S3?

Next Generation Network-on-Chip (NoC) Interconnect for Armv9-A SoCs

NoC S3 is the next generation non-coherent Arm Network-on-Chip (NoC) interconnect, designed to meet the growing complexity of heterogeneous System-on-Chips (SoCs). It delivers high bandwidth, low-latency and low-power connectivity between SoC components with flexible topologies that can scale to the widest range of SoC designs and cost points.

 

The interconnect has been optimized alongside Armv9-A processors and supports the latest AMBA interfaces to provide the ideal SoC backplane for a wide range of SoC designs.

 

Design for Armv9-A CPUs

Designed and validated alongside the latest Armv9-A CPUs for optimum system compatibility and performance.
Configurable Topologies, Designed to Scale

NoC S3 supports a wide range of topologies supporting use cases from infrastructure solutions to smartphone and IoT devices.

Tooling for Automated NoC Design and optimization

Fast NoC design and implementation through a complementary tooling solution as part of the product. Automated physical-aware NoC design, with built-in optimization to achieve design goals with best PPA.
Better PPA

NoC S3 delivers new features for increased performance, reduced power, reduced area and increased bandwidth.
Greater Design Flexibility

NoC S3 enables greater design flexibility through new programmable address map.
Enhanced Security and System Reliability

NoC S3 supports Realm Management Extension (RME) to enable Confidential Compute as part of Neoverse platform, alongside new memory protection mechanism and RAS (reliability, accessibility, serviceability) features.

Arm Interconnect Network on Chip S3 Block Diagram
SPECIFICATIONS

NoC S3 Specifications

NoC S3 is a high bandwidth, low-latency and low-power interconnect designed for a wide range of Arm-based SoCs. It supports up to 255 network interfaces, flexible topology configurations, and the latest AMBA protocols including AXI5, ACE5-Lite, and AXI-Stream, making it ideal for AI-capable mobile, infrastructure, and IoT deployments

View Arm Developer for more details.

TOOLING HIGHLIGHTS

Accelerated NoC Design with Built-In Optimization

Faster Time to Market icon

Fewer Design Cycles and Faster Time to Market

Speedometer icon

Achieve Design Goals with Most PPA Optimized Topologies

Engineering Resource icon

Intuitive NoC Specification and Design Workflow

FEATURES

Key Capabilities

Support for Script and GUI-driven Workflows

API-driven tooling for ultra-fast execution enables flexibility and customization. Visualize floor plan and NoC layout with GUI application built on top of the API for increased user productivity.
Floorplan-aware Design & Timing Closure Support

Physical-aware GUI considers blockages, devices, and unrouteable areas to simplify P&R and timing closure. This reduces routing congestion, places the NoC within SoC to aid timing closure. Integrated placement engine facilitates timing closure with automated slack reduction and pipeline insertion.
Automatic NoC Generation with Built-in Optimization

NoC-SE synthesize engine automatically generates NoC topologies from high-level specification input. Cell area and wire optimization with embedded cost model and ML based area prediction helps achieve balance between performance and cost during topology creation.
Intuitive Traffic Specification

Use-case based traffic specification reduces effort needed to design bigger NoCs.
Achieve Performance with Ease 

Advanced Head-of-line (HoL) and deadlock avoidance mechanisms, plus efficient use of virtual channels as part of topology generation help meeting performance requirements of complex heterogeneous designs. Early performance feedback is provided through performance model.
USE CASES

Optimized for Every SoC Application

Consumer Devices

NoC S3 is a scalable, energy-efficient, non-coherent interconnect designed to meet the diverse SoC connectivity needs of consumer devices, from wearables to digital TVs and mass-market smartphones. It enables seamless integration of compute, media, AI, and connectivity components in a SoC. With its flexible architecture, NoC S3 supports a broad range of SoC designs, helping partners optimize for performance, power, and cost across their consumer device portfolios.

Learn More

Infrastructure

NoC S3 addresses the rigorous performance and reliability demands of modern infrastructure solutions, including datacenters, networking equipment, and cloud-edge computing systems. Its flexible topologies and optimized QoS management enable high throughput, low latency, and robust security for mission-critical infrastructure workloads.

Learn More

IoT

NoC S3 provides IoT devices with an ultra-efficient and secure interconnect solution tailored for smart homes, industrial IoT, and smart city deployments. Its low-power design, robust security capabilities, and scalability make it ideal for managing heterogeneous workloads and connectivity across diverse IoT ecosystems.

Learn More
RELATED PRODUCTS

Explore Related Interconnect Solutions

System Interconnect SI L1

Arm SI L1

Explore how SI L1 interconnect enables scalable coherency for high performance smartphone and LSC SoCs as part of the Arm Lumex CSS platform. Optimized for smartphone and large screen compute (LSC) designs, it provides a low-latency, low-power interconnect solution for AI- ready systems.

Explore Arm SI L1

Neoverse CMN S3

Discover how Neoverse CMN S3 delivers high-bandwidth, coherent interconnect for infrastructure-class compute—optimized for cloud, 5G, and AI workloads across the data center to edge.

Explore CMN S3
CoreLink Network Interconnect

Network Interconnect (NIC) Family

Discover how NIC-400 and NIC-450 deliver low-latency, crossbar-based AMBA interconnects—ideal for cost-sensitive SoCs requiring configurable AXI, AHB, and APB connectivity with low area and power overhead.

Explore Interconnect Solutions

Talk with an Expert

Still unsure which Interconnect product is right for your SoC project? Talk to an Arm expert and learn more.

Contact Us